1. Technical Field
The present invention relates to data processing systems, and in particular to the efficient management of a plurality of physical registers in a superscalar data processing system. Still more particularly, the present invention relates to a method and system in a superscalar data processing system for the temporary designation of one of a plurality of physical registers as a general register, wherein none of the physical registers were initially designated as a general register.
2. Description of the Related Art
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required. Instructions are first fetched and then decoded. The overlap of the fetching and decoding of one instruction with the execution of a second instruction is called pipelining. In pipelined superscalar data processing systems, care must be taken to avoid dependencies where multiple instructions are fetched, decoded, and executed in a single cycle.
Software, written to load, store, and perform other operations, utilizes logical register names. These logical register names identify particular general registers. Typically, there are eight general registers which may be identified by software. In known systems, general purpose architectural registers, also called general registers, exist separate and apart from other registers which may also be included such as special purpose registers, and rename registers. These general registers are initially associated with a particular logical register name.
For example, one of the general purpose registers may be designated as general register 2 and be associated with a logical register name of "2". A typical software instruction may attempt to load data into general register 2. This instruction may be written: LOAD 2,data1. When processing this instruction, a copy of the data stored in storage location data1 will be loaded into the general register designated as general register 2. In such systems, any time an instruction is associated with a logical register name of "2", it will utilize the general register designated as general register 2.
Each general register included in these systems is designated as a particular general register. Often there may be eight general registers in a system. In this case, the general registers may be designated as general register 1 through general register 8. These general register designations exist in hardware and are therefore determined prior to the system ever being powered on. These designations never change. A general register designated as general register 1 will always be designated as general register 1. Further, no other general register can ever be designated as general register 1.
When multiple instructions are to be processed during a single clock cycle, a conflict may exist when two or more of these instructions attempt to utilize the same general register. For example, the following instruction sequence may need to be concurrently processed:
Instruction N1: LOAD 2, data1 PA1 Instruction N2: ADD REG 2,3 PA1 Instruction N3: STORE 2, temp PA1 Instruction N4: LOAD 2, data2
A conflict arises during scheduling of these instructions because both instructions N1 and N4 load different data into general register 2. The instructions may be scheduled such that instruction N4 destroys the result from instruction N2 before instruction N3 had a chance to put the result into storage location "temp".
Therefore a need exists for a method and system in a superscalar data processing system for temporarily designating one of a plurality of physical registers as a general register, where none of the physical registers were initially designated as a general register.